Field effect transistors (FETs) have inherent device resistance, including parasitic resistances, which may be modeled as a resistor in series with the switch. Performance depends upon how fast the circuit can charge and discharge the capacitive load, i.e., the circuit's switching speed. Device resistances limit current supplied by a particular device and slow capacitive switching. Thus, how fast the circuit switches the particular load depends both upon device on-current (e.g., which is selected by design) and the device resistances. Thus, circuit performance is maximized by maximizing device on-current and minimizing unwanted device resistance.
Another design concern is that, as FET features have shrunk, what are collectively known as short channel effects have become more pronounced, resulting in a rapid increase of static power consumption. Short channel effects have occurred, in part, from a threshold voltage reduction as the FET gate length is reduced. Such threshold voltage dependence on gate length, also known as threshold voltage roll-off, has been mitigated by thinning the transistor gate insulator (e.g., silicon oxide (SiO2), a high-K dielectric). Unfortunately, especially as FET features have shrunk, thinner gate insulator has resulted in increased gate leakages or gate induced leakages (e.g., gate to channel, gate to source or drain and gate induced drain leakage (GIDL)). Therefore, for circuits with transistor gate lengths shorter than 100 nm, the circuit stand-by power has become comparable to the active power.
Short channel effects are known to improve inversely with channel thickness. For silicon on insulator (SOI) semiconductor devices, sub-threshold leakage and other short channel effects have been controlled and reduced by thinning the surface silicon layer, i.e., the device channel layer. Fully depleted (FD) devices (e.g., FDSOI devices) or partially depleted (PD) devices (e.g., PDSOI devices) have been formed in ultrathin SOI and/or extremely-thin SOI (ETSOI), for example, where the silicon channel layer is less than 50 nm or, in some cases, less than 20 nm. Ultrathin FDSOI devices operate at lower effective voltage fields. Additionally, these ultrathin SOI layers can be doped for higher mobility, which in turn increases device current and improves circuit performance. Furthermore, ultrathin FDSOI devices have a steeper sub-threshold current swing with current falling off sharply as the gate to source voltage drops below the threshold voltage.
Unfortunately, however, forming source/drain (S/D) regions that are made from the same ultrathin silicon layer increases external resistance and, in particular, contact resistance. Similar high resistance S/D diffusion and contact problems have been encountered in bulk silicon complementary metal oxide semiconductor (CMOS) devices with lightly doped drain (LDD) devices, where the S/D regions are maintained very shallow for lower voltage operation. Silicide has been tried to reduce this external resistance but has not been problem free. Especially for these very short devices, unless the S/D silicide is spaced away from the gate, the silicide can cause gate to channel or S/D shorts, for example. In addition, silicide can interfere or interact with high-K gate dielectric formation and vice versa.